1. Field of the Invention
This invention relates to a semiconductor device and manufacturing method therefor, and particularly to technology useful for easily effecting high functionality in semiconductor devices comprising a semiconductor element or elements (chip or chips) mounted in a package.
2. Description of the Related Art
Various forms have been proposed for semiconductor devices constituted by mounting a semiconductor element or elements in a package. One example thereof is a semiconductor device wherein a plurality of semiconductor chips is mounted on one substrate to achieve higher integration and higher functionality.
Specific forms of such a semiconductor device which are known include, for example, those wherein semiconductor chips are mounted respectively on both sides of the substrate, those wherein semiconductor chips are stacked on one side of the substrate, and those wherein a plurality of semiconductor chips is mounted inside the surfaces of the substrate.
In every one of these forms, a wiring pattern is suitably formed on the surface of the substrate, to which wiring patterns the electrode pads (terminals) of the semiconductor chips are electrically connected by wire bonding.
Of course, the electrical connections between the semiconductor chips and the wiring patterns are not limited to wire bonding connections, and flip chip connections and TAB connections and the like can also be used.
In the conventional semiconductor devices described above, because the semiconductor chips are mounted on the substrate mounting surface, the fact that substrates are made in prescribed sizes means that the number of semiconductor chips that can be mounted is limited, which is a disadvantage.
Also, when semiconductor chips are mounted in a stack, it is necessary to make the upper chips smaller in size than the lower chips by an amount equal to the area which is needed to make the wire bonding connections. Hence the mounting area of the upper chip or chips becomes narrow, and there is inherently a limit to the number of chips that can be stacked up.
In this case, when flip chip connections are used, there is no need to provide room for bonding as described above, for which reason, it is possible to increase the number of chip mountings compared to when wire bonding connections are used, but other difficulties arise.
In general, with flip chip mounting, bumps (electrode terminals) made of solder or other metals are formed on the electrode pads of the semiconductor chips, and connections are effected by thermally pressing these bumps down on top of corresponding electrode pads on the printed circuit board or other mounting substrates.
When this approach is applied to layered forms of chips, the upper chip will be flip-chip connected to the lower chip.
In such cases, it is necessary to form electrode pads on the upper surface of the lower chip in such a way that they correspond to the positions of the bumps that are the electrode terminals of the upper chip. Furthermore, when the chips are stacked, the positions of the bumps on the upper chips and the electrode pads on the lower chips must be aligned, resulting in the disadvantage that the overall process becomes complex.
In such a conventional semiconductor device as this, because the semiconductor chips are simply mounted on the mounting surface of the substrate, the number of semiconductor chips mounted is limited, and it is not always possible to realize adequately high functionality or the like, which is a problem.
Also, because the semiconductor chips are mounted in a form in which they are externally attached to the substrate, another disadvantage arises in that the overall semiconductor device becomes relatively thick.
Meanwhile, semiconductor device designs which are different from those of the conventional form described in the foregoing, have been conceived in which the substrate is made multi-layered and the semiconductor chips are placed inside the substrate, in order to achieve even higher integration and higher functionality.
For example, if a multi-layer substrate structure is used which is provided with a plurality of wiring layers, it is possible to electrically interconnect the semiconductor chips and place them three-dimensionally inside the substrate.
However, not only is it not necessarily easy to implant semiconductor chips inside a substrate and form the wiring layers as multiple layers but when consideration is given to the recent demand for packages to be smaller and lighter in weight, there is the problem of having to reduce the overall thickness and make the semiconductor device more compact.